Hardware Guide

STM32F7 for Image Classification with TensorFlow Lite Micro

For image classification, the STM32F7 with TFLite Micro scores Excellent. Its 512 KB internal SRAM (4.0x the required 128 KB) and 216 MHz clock ensure smooth real-time inference on 150 KB models. Hardware DSP extensions boost throughput.

Compatibility: Excellent

Memory-wise, the STM32F7 offers 512 KB SRAM, which provides 4.0x the 128 KB minimum for image classification. This generous headroom means the 150 KB model tensor arena, sensor input buffers, and application logic (camera polling, Ethernet stack, state management) all fit without contention. The remaining 137 KB after model allocation supports complex application features. For firmware and model storage, the 2 MB flash comfortably houses the TFLite Micro runtime, the 150 KB model binary, application firmware, and OTA update partitions for field upgrades. Flash usage is well within budget for this configuration. The STM32F7 at 216 MHz with Cortex-M7 instruction and data caches delivers near-real-time inference for mid-size models. Its 512 KB SRAM handles most sensor and audio ML workloads. The ART accelerator reduces flash access latency during inference. For image classification, connect a camera module (e.g., OV2640 via DVP/SPI) via SPI to the STM32F7. The camera interface supports QVGA (320×240) or lower resolution for on-device inference. Downsample to the model's input size (typically 48×48 to 96×96 pixels) before feeding the neural network. TFLite Micro's static memory allocation model maps well to the STM32F7's memory architecture — define a fixed tensor arena at compile time with no runtime heap fragmentation risk. The framework's operator coverage supports convolutional, depthwise-separable, and pooling layers needed for image classification. Model conversion uses the standard TFLite converter with int8 post-training quantization. At $8-15 per chip ($25-60 for dev boards), the STM32F7 offers strong value for image classification deployments. Key STM32F7 features for this workload: Double-precision FPU, L1 cache (16 KB I + 16 KB D), ART Accelerator, Chrom-ART (DMA2D), TFT-LCD controller.

Alternatives

FAQ

What camera resolution works for image classification on STM32F7?

On-device image classification models typically use 48×48 to 96×96 pixel grayscale input. The STM32F7's 512 KB SRAM constrains this: a 96×96 grayscale frame is ~9 KB, while 128×128 RGB would need ~49 KB. The native camera interface (DVP/DCMI) handles frame capture efficiently. Always downsample in firmware before inference.

How do I update the image classification model on STM32F7 in production?

Without wireless connectivity, model updates require physical access via USB/JTAG. For field deployments, consider adding a wireless module or using an MCU with built-in connectivity. Always validate model integrity with a checksum before switching to the new version.

What size image classification model fits on STM32F7?

The STM32F7 has 512 KB SRAM and 2 MB flash. A typical image classification model is 150 KB after int8 quantization. The tensor arena needs 225-300 KB at runtime. After model allocation, approximately 212 KB remains for application logic, sensor drivers, and Ethernet stack.