Hardware Guide

RA6M5 for People Counting with CMSIS-NN

Renesas's RA6M5 is a solid choice for people counting using CMSIS-NN. The cortex-m33 core at 200 MHz with 512 KB SRAM accommodates 200 KB models with room for application logic. DSP extensions available.

Hardware Specs

Spec RA6M5
Processor ARM Cortex-M33 @ 200 MHz
SRAM 512 KB
Flash 2 MB
Key Features TrustZone hardware security, Renesas Secure Crypto Engine (SCE9), High-speed Cortex-M33 (200 MHz), QSPI for external memory expansion
Connectivity Ethernet, USB HS
Price Range $6 - $12 (chip), $25 - $50 (dev board)

Compatibility: Good

With 512 KB of internal SRAM, the RA6M5 delivers 2.7x the 192 KB minimum needed for people counting. The 200 KB quantized model fits in the tensor arena with enough remaining capacity for input buffers and core application logic. More demanding features (multi-sensor fusion, large protocol stacks) may require careful allocation planning. The RA6M5 provides 2 MB of flash memory, which accommodates the CMSIS-NN runtime and 200 KB model. Space remains for firmware and basic OTA capability. The RA6M5 at 200 MHz combines Cortex-M33 with TrustZone, a crypto engine, and 512 KB SRAM. Renesas Reality AI adds vibration and time-series anomaly detection as a turnkey solution. The RA6M5 targets industrial and IoT ML applications with built-in security. People Counting requires camera input. The RA6M5 lacks native peripheral support for some of these sensors, requiring external interface circuitry. A camera interface (DVP/DCMI) is not available — SPI-based camera modules may work but with reduced frame rates. Evaluate whether the peripheral gap justifies an alternative MCU with native support. CMSIS-NN provides ARM-optimized neural network kernels that leverage the RA6M5's DSP instructions and floating-point unit for maximum inference throughput on Cortex-M. The kernels are hand-optimized in assembly for critical operations (Conv2D, DepthwiseConv2D, FullyConnected). Combine with TFLite Micro's CMSIS-NN delegate for the best performance on ARM targets. At $6-12 per chip ($25-50 for dev boards), the RA6M5 is a reasonable investment for people counting deployments. Key RA6M5 features for this workload: TrustZone hardware security, Renesas Secure Crypto Engine (SCE9), High-speed Cortex-M33 (200 MHz), QSPI for external memory expansion.

Getting Started

  1. 1

    Set up RA6M5 development environment

    Install e2 studio with Renesas FSP (Flexible Software Package). Create a project targeting the RA6M5 and verify basic functionality (blink LED, serial output). For CMSIS-NN, clone the framework repository and add it as a library dependency. Ensure the toolchain supports C++11 or later for the ML runtime.

  2. 2

    Collect camera training data

    Connect a camera module (e.g., OV2640 via DVP/SPI) to the RA6M5. Write a data logging sketch that captures camera readings at the target sample rate and outputs via serial/SD card. Collect 1000+ labeled samples across all classes. Capture images at the model input resolution (96×96 or lower).

  3. 3

    Train model and prepare for CMSIS-NN deployment

    Train a quantized MobileNet-SSD or YOLO-Tiny in TensorFlow/Keras. Apply int8 post-training quantization via the TFLite converter — this is essential for CMSIS-NN's optimized kernels. The quantized model should be under 200 KB. Use tflite_micro's CMSIS-NN delegate to automatically route operations to optimized ARM kernels on the RA6M5's cortex-m33 core.

  4. 4

    Deploy and validate on RA6M5

    Include the CMSIS-NN runtime and compiled model in your Renesas project. Allocate a tensor arena of 300-500 KB in a static buffer. Run inference on live camera data and compare predictions against your test set. Log results to serial for desktop validation. Measure inference latency and peak RAM usage to verify they meet application requirements.

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FAQ

What size people counting model fits on RA6M5?
The RA6M5 has 512 KB SRAM and 2 MB flash. A typical people counting model is 200 KB after int8 quantization. The tensor arena needs 300-400 KB at runtime. After model allocation, approximately 112 KB remains for application logic, sensor drivers, and Ethernet stack.
Why choose CMSIS-NN over other frameworks for RA6M5?
CMSIS-NN provides optimized inference on RA6M5's Cortex-M33 core. Its hand-optimized assembly kernels for Conv2D, DepthwiseConv2D, and FullyConnected operations are specifically tuned for Cortex-M architectures. The DSP instructions are utilized by CMSIS-NN's SIMD kernels for additional speedup. Use TFLite Micro with the CMSIS-NN delegate to combine broad operator support with ARM-optimized performance.
Can RA6M5 run people counting inference in real time?
The RA6M5 runs at 200 MHz with DSP acceleration. Whether this enables real-time people counting depends on your specific model architecture and acceptable latency. A 200 KB int8 model is a reasonable target for this hardware class. Larger models may require duty-cycled inference or model optimization (pruning, distillation). Benchmark your specific model on hardware to validate timing.

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