Hardware Guide
i.MX RT1062 for People Counting with CMSIS-NN
NXP's i.MX RT1062 excels at people counting via CMSIS-NN. The 1-core cortex-m7 at 600 MHz with 1024 KB SRAM handles 200 KB quantized models with 5.3x RAM headroom. Built-in Ethernet enables wireless result reporting.
Published 2026-04-02
Hardware Specs
| Spec | i.MX RT1062 |
|---|---|
| Processor | ARM Cortex-M7 @ 600 MHz |
| SRAM | 1024 KB |
| Flash | Up to 8 MB (external) |
| Key Features | Crossover MCU (600 MHz Cortex-M7), 1 MB on-chip SRAM (double of RT1052), L1 cache (32 KB I + 32 KB D), FlexRAM (configurable ITCM/DTCM/OCRAM), No on-chip flash (external QSPI/HyperFlash) |
| Connectivity | Ethernet, USB OTG HS/FS |
| Price Range | $6 - $12 (chip), $25 - $40 (dev board) |
Compatibility:
With 1024 KB of internal SRAM, the i.MX RT1062 provides 5.3x the 192 KB minimum for people counting. This generous headroom means the 200 KB model tensor arena, sensor input buffers, and application logic (camera polling, Ethernet stack, state management) all fit without contention. The remaining 524 KB after model allocation supports complex application features. The i.MX RT1062 provides 8 MB of flash memory, which comfortably houses the CMSIS-NN runtime, the 200 KB model binary, application firmware, and OTA update partitions for field upgrades. Flash usage is well within budget for this configuration. The i.MX RT1062 runs at 600 MHz on a Cortex-M7 core, placing it among the higher-performance MCU options for ML inference. Its 1 MB SRAM and external memory interface support larger models including small vision networks. NXP's eIQ ML software provides optimized kernels for the RT series. People Counting requires camera input. The i.MX RT1062 lacks native peripheral support for some of these sensors, requiring external interface circuitry. A camera interface (DVP/DCMI) is not available — SPI-based camera modules may work but with reduced frame rates. Evaluate whether the peripheral gap justifies an alternative MCU with native support. CMSIS-NN provides ARM-optimized neural network kernels that leverage the i.MX RT1062's DSP instructions and floating-point unit for maximum inference throughput on Cortex-M. The kernels are hand-optimized in assembly for critical operations (Conv2D, DepthwiseConv2D, FullyConnected). Combine with TFLite Micro's CMSIS-NN delegate for the best performance on ARM targets. At $6-12 per chip ($25-40 for dev boards), the i.MX RT1062 offers strong value for people counting deployments. Key i.MX RT1062 features for this workload: Crossover MCU (600 MHz Cortex-M7), 1 MB on-chip SRAM (double of RT1052), L1 cache (32 KB I + 32 KB D), FlexRAM (configurable ITCM/DTCM/OCRAM), No on-chip flash (external QSPI/HyperFlash).
Getting Started
- 1
Set up i.MX RT1062 development environment
Install MCUXpresso IDE with the MCUXpresso SDK. Create a project targeting the i.MX RT1062 and verify basic functionality (blink LED, serial output). For CMSIS-NN, clone the framework repository and add it as a library dependency. Ensure the toolchain supports C++11 or later for the ML runtime.
- 2
Collect camera training data
Connect a camera module (e.g., OV2640 via DVP/SPI) to the i.MX RT1062. Write a data logging sketch that captures camera readings at the target sample rate and outputs via serial/SD card. Collect 1000+ labeled samples across all classes. Capture images at the model input resolution (96×96 or lower).
- 3
Train model and prepare for CMSIS-NN deployment
Train a quantized MobileNet-SSD or YOLO-Tiny in TensorFlow/Keras. Apply int8 post-training quantization via the TFLite converter — this is essential for CMSIS-NN's optimized kernels. The quantized model should be under 200 KB. Use tflite_micro's CMSIS-NN delegate to automatically route operations to optimized ARM kernels on the i.MX RT1062's cortex-m7 core.
- 4
Deploy and validate on i.MX RT1062
Include the CMSIS-NN runtime and compiled model in your NXP project. Allocate a tensor arena of 300-500 KB in a static buffer. Run inference on live camera data and compare predictions against your test set. Log results to serial for desktop validation. Measure inference latency and peak RAM usage to verify they meet application requirements.
Alternatives
STM32H7 with CMSIS-NN
STMicroelectronics cortex-m7 at 480 MHz with 1024 KB SRAM. $8-20 per chip. Excellent rated.
STM32F7 with CMSIS-NN
STMicroelectronics cortex-m7 at 216 MHz with 512 KB SRAM. $8-15 per chip. Compared to i.MX RT1062: less RAM but lower cost. Good rated.
STM32U5 with CMSIS-NN
STMicroelectronics cortex-m33 at 160 MHz with 786 KB SRAM. $6-15 per chip. Good rated.
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FAQ
- Can i.MX RT1062 run people counting inference in real time?
- The i.MX RT1062 runs at 600 MHz with DSP acceleration. Whether this enables real-time people counting depends on your specific model architecture and acceptable latency. A 200 KB int8 model is a reasonable target for this hardware class. Larger models may require duty-cycled inference or model optimization (pruning, distillation). Benchmark your specific model on hardware to validate timing.
- What is the power consumption for people counting on i.MX RT1062?
- Power consumption during inference depends on clock configuration, active peripherals, and duty cycle. Consult the i.MX RT1062 datasheet for detailed power profiles at 600 MHz. For battery-powered people counting, use duty cycling: run inference at intervals and enter low-power sleep mode between cycles. Profile your specific workload to estimate battery life accurately.
- What camera resolution works for people counting on i.MX RT1062?
- On-device people counting models typically use 96×96 or 128×128 pixel grayscale input. The i.MX RT1062's 1024 KB SRAM constrains this: a 96×96 grayscale frame is ~9 KB, while 128×128 RGB would need ~49 KB. Without a native camera interface, use an SPI camera module (e.g., ArduCAM Mini) with reduced frame rates. Always downsample in firmware before inference.
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