Hardware Guide

STM32H7 for Image Classification with CMSIS-NN

The STM32H7 is an excellent match for image classification with CMSIS-NN. 1024 KB SRAM delivers 8.0x the 128 KB minimum while 480 MHz processes 150 KB models in real time. DSP extensions and double-precision FPU accelerate inference.

Hardware Specs

Spec STM32H7
Processor ARM Cortex-M7 @ 480 MHz
SRAM 1024 KB
Flash 2 MB
Key Features Double-precision FPU, L1 cache (16 KB I + 16 KB D), JPEG codec, Chrom-ART Accelerator (DMA2D)
Connectivity Ethernet, USB OTG HS/FS
Price Range $8 - $20 (chip), $30 - $80 (dev board)

Compatibility: Excellent

At 1024 KB SRAM, the STM32H7 provides 8.0x the 128 KB minimum for image classification. This generous headroom means the 150 KB model tensor arena, sensor input buffers, and application logic (camera polling, Ethernet stack, state management) all fit without contention. The remaining 649 KB after model allocation supports complex application features. Flash storage at 2 MB comfortably houses the CMSIS-NN runtime, the 150 KB model binary, application firmware, and OTA update partitions for field upgrades. Flash usage is well within budget for this configuration. The STM32H7 at 480 MHz with double-precision FPU and ART accelerator is among the highest-performance Cortex-M MCUs in ST's lineup. Its 1 MB SRAM accommodates models that smaller MCUs cannot fit in memory. Dual-bank flash enables safe OTA firmware updates during operation. For image classification, connect a camera module (e.g., OV2640 via DVP/SPI) via SPI to the STM32H7. The camera interface supports QVGA (320×240) or lower resolution for on-device inference. Downsample to the model's input size (typically 48×48 to 96×96 pixels) before feeding the neural network. CMSIS-NN provides ARM-optimized neural network kernels that leverage the STM32H7's DSP instructions and floating-point unit for maximum inference throughput on Cortex-M. The kernels are hand-optimized in assembly for critical operations (Conv2D, DepthwiseConv2D, FullyConnected). Combine with TFLite Micro's CMSIS-NN delegate for the best performance on ARM targets. At $8-20 per chip ($30-80 for dev boards), the STM32H7 offers strong value for image classification deployments. 22 PlatformIO-listed boards provide decent hardware selection. Key STM32H7 features for this workload: Double-precision FPU, L1 cache (16 KB I + 16 KB D), JPEG codec, Chrom-ART Accelerator (DMA2D).

Getting Started

  1. 1

    Set up STM32H7 development environment

    Install STM32CubeIDE with the latest STM32Cube firmware package. Create a project targeting the STM32H7 and verify basic functionality (blink LED, serial output). For CMSIS-NN, clone the framework repository and add it as a library dependency. Ensure the toolchain supports C++11 or later for the ML runtime.

  2. 2

    Collect camera training data

    Connect a camera module (e.g., OV2640 via DVP/SPI) to the STM32H7. Write a data logging sketch that captures camera readings at the target sample rate and outputs via serial/SD card. Collect 1000+ labeled samples across all classes. Capture images at the model input resolution (96×96 or lower).

  3. 3

    Train model and prepare for CMSIS-NN deployment

    Train a quantized MobileNetV2 or EfficientNet-Lite in TensorFlow/Keras. Apply int8 post-training quantization via the TFLite converter — this is essential for CMSIS-NN's optimized kernels. The quantized model should be under 150 KB. Use tflite_micro's CMSIS-NN delegate to automatically route operations to optimized ARM kernels on the STM32H7's cortex-m7 core.

  4. 4

    Deploy and validate on STM32H7

    Include the CMSIS-NN runtime and compiled model in your STMicroelectronics project. Allocate a tensor arena of 225-375 KB in a static buffer. Run inference on live camera data and compare predictions against your test set. Log results to serial for desktop validation. Measure inference latency and peak RAM usage to verify they meet application requirements.

Alternatives

STM32F7 with CMSIS-NN

STMicroelectronics cortex-m7 at 216 MHz with 512 KB SRAM. $8-15 per chip. Compared to STM32H7: less RAM but lower cost. Excellent rated.

i.MX RT1062 with CMSIS-NN

NXP cortex-m7 at 600 MHz with 1024 KB SRAM. $6-12 per chip. Compared to STM32H7: cheaper. Excellent rated.

RA6M5 with CMSIS-NN

Renesas cortex-m33 at 200 MHz with 512 KB SRAM. $6-12 per chip. Compared to STM32H7: less RAM but lower cost, cheaper. Good rated.

Explore More

More STM32H7 guides More Image Classification guides All resources Find the right MCU

FAQ

Can STM32H7 run image classification inference in real time?
The STM32H7 runs at 480 MHz with DSP acceleration. Whether this enables real-time image classification depends on your specific model architecture and acceptable latency. A 150 KB int8 model is a reasonable target for this hardware class. Larger models may require duty-cycled inference or model optimization (pruning, distillation). Benchmark your specific model on hardware to validate timing.
What is the power consumption for image classification on STM32H7?
Power consumption during inference depends on clock configuration, active peripherals, and duty cycle. Consult the STM32H7 datasheet for detailed power profiles at 480 MHz. For battery-powered image classification, use duty cycling: run inference at intervals and enter low-power sleep mode between cycles. Profile your specific workload to estimate battery life accurately.
What camera resolution works for image classification on STM32H7?
On-device image classification models typically use 48×48 to 96×96 pixel grayscale input. The STM32H7's 1024 KB SRAM constrains this: a 96×96 grayscale frame is ~9 KB, while 128×128 RGB would need ~49 KB. The native camera interface (DVP/DCMI) handles frame capture efficiently. Always downsample in firmware before inference.

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